The fabrication of semiconductor devices involves the formation of a number of different layers over a semiconductor substrate or wafer. The various layers include conductive layers, such as doped polysilicon or metal layers, and dielectric layers which are used to insulate the conductive layers. One important step in fabricating a device is polishing or planarization. Planarization or planarizing generally involves removing material from a layer in order to provide the layer with a more level or planar surface. The need for planarity stems from subsequent processes, such as photolithography, the results of which are highly dependent upon the planarity of the wafer.
A number of different techniques may be used to planarize wafers. One common technique for planarizing silicon dioxide as well as other types of surfaces on semiconductor wafers is chemical-mechanical polishing (CMP). Chemical mechanical polishing typically utilizes an abrasive slurry disbursed in an alkaline or acidic solution to planarize the surface of the wafer through a combination of mechanical and chemical action. One type of chemical mechanical polishing (CMP) system includes a rotatable circular platen or table on which a polishing pad is mounted. A single or multi-head polishing device is positioned above the table. The polishing device has a single or multiple rotating carrier heads to which wafers can be secured typically through the use of vacuum pressure. In use, the platen is rotated and an abrasive slurry is disbursed onto the polishing pad of the platen. Once the slurry has been applied to the polishing pad, the rotating carrier heads move downward to press their corresponding wafers against the polishing pad. As a wafer is pressed against the polishing pad, the surface of the wafer is mechanically and chemically planarized.
The surface of the layer being planarized is generally associated with hills and valleys depending on the underlying topography. The goal of planarization is to level this surface by removing material forming the hills. The effectiveness or efficiency of a planarization process is typically a function of process parameters, such as the downforces on the polishing arms, the polishing table speed, the polishing time, the pad, and the slurry, and the width and depth of the valleys.
Conventional techniques for measuring the efficiency of a planarization process generally use a substrate having patterned metal lines. In these techniques, a layer of metal is deposited over a substrate, patterned with a photoresist mask and then etched to form isolated metal lines of varying width. A layer of silicon dioxide is then formed over the patterned metal lines. Due to the metal line features, the silicon dioxide layer will include hills over the metal lines and valleys in between metal lines. The thickness of the silicon dioxide is measured in the hills and valleys. The silicon dioxide layer is then polished and the post-polish thickness of the silicon dioxide layer is measured. The planarization efficiency (P.sub.eff) of the process may then be calculated using the relationship: ##EQU1##
where R.sub.valley is the removal amount or rate in the valleys and R.sub.hill is the removal amount or rate in the hills. As it is generally desired to remove material only from the hills and as little material as possible from the valleys, higher values of P.sub.eff signify better planarization efficiency. While conventional techniques can provide a measure of planarization efficiency, manufacturers continue to search for techniques which provide more accurate planarization efficiency measurement, reduce the expense of planarization efficiency measurement and/or the time needed to perform the measurement.